1. Field of the Invention
The present invention relates to a first-in first-out memory device (hereinafter referred to as "FIFO memory device"), and more particularly, it relates to an FIFO memory device having data enlargement and reduction functions.
2. Description of the Background Art
FIG. 58 is a block diagram showing the structure of a conventional FIFO memory device having a data enlargement/reduction function. Referring to this figure, numeral 21 denotes an FIFO memory part which is capable of writing/reading data, numeral 22 denotes a write data reduction control circuit for reducing write data WD written in the FIFO memory part 21, and numeral 23 denotes a read data enlargement control circuit for enlarging read data RD read from the FIFO memory part 21. The FIFO memory part 21, the write data reduction control circuit 22 and the read data enlargement control circuit 23 form the FIFO memory device, which is capable of enlarging/reducing data.
In the FIFO memory part 21, numeral 12 denotes a memory cell matrix which is formed by a plurality of memory cells for storing data, numeral 13 denotes a write clock counter for counting write clocks WK1 received therein, numeral 14 denotes a write address decoder which receives count values outputted from the write clock counter 13 for specifying addresses of the memory cell matrix 12 for writing data with the count values serving as address data, and numeral 15 denotes a write data driver which writes data WD received through the write data reduction control circuit 22 in the memory cell matrix 12. Further, numeral 16 denotes a read clock counter for counting read clocks RK1 inputted therein, numeral 18 denotes a read address decoder which receives count values outputted from the read clock counter 16 for specifying addresses of data to be read from those held in the memory cell matrix 12 with the count values serving as address data, and numeral 19 denotes a read data sense amplifier for reading data from the memory cell matrix 12 and converting the same to digital signals.
Operations of the FIFO memory device are now described. In the case of data reduction, data, which is assumed to be "00011011", for example, inputted from an input terminal SVDI of the FIFO memory device is incorporated in the data reduction control circuit 22 in synchronization with a clock SCLK which is inputted in the write data reduction control circuit 22. Assuming that the data reduction ratio is 0.5 (only data inputted in odd times are employed as write data), the data "00011011" inputted in the write data control circuit 22 is reduced to "0011" as write data WD and outputted. The write data driver 15 writes the as-received write data WD in the memory cell matrix 12 in response to a write clock WK1. Further, the write clock WK1 outputted from the write data reduction control circuit 22 is inputted in the write clock counter 13, and the write address decoder 14 decodes the count value outputted from the write clock counter 13 and outputs the decode output to the memory cell matrix 12. The memory cell matrix 12 selects a corresponding 1 -bit memory cell every such decode input, so that the write data driver 15 writes the write data WD in the selected memory cell.
A case of data enlargement is now described in relation to enlargement of the data "00011011" held in the memory cell matrix 12 in a data enlargement ratio of 2, for example. A read clock RK1 outputted from the read data enlargement control circuit 23 is inputted in the read clock counter 16. The read address decoder 18 decodes the count value of the read clock RK1 outputted from the read clock counter 16, and outputs the decode output to the memory cell matrix 12. The memory cell matrix 12 selects a corresponding 1-bit memory cell every such decode input, so that the read data sense amplifier 19 reads out the data held in the selected memory cell in response to the read clock RK1. The read data sense amplifier 19 converts the read data to a digital signal and outputs read data RD, such as "00011011", for example, to the read data enlargement control circuit 23. The read data enlargement control circuit 23 enlarges the as-received read data RD "00011011", to output enlarged data "0000001111001111" from an output terminal RVDO of the FIFO memory device in synchronization with a clock TCLK received in the read enlargement control circuit 23.
FIGS. 59(a) and 59(b) are timing charts showing operations of the write data reduction control circuit 22 and the read data enlargement control circuit 23 shown in FIG. 58 respectively. In response to the write clock WK1, the write data reduction control circuit 22 outputs only odd data among those received from the input terminal SVD1 in response to the clock SCLK as shown in FIG. 59(a), thereby reducing the data. On the other hand, the read data enlargement control circuit 23 outputs as-received 1-bit read data RD from the output terminal RVDO twice by the clock TCLK in response to the read clock RK1 as shown in FIG. 59(b), thereby enlarging the data to twice.
In general, data are reduced by the write data reduction control circuit 22 when the same are written in the FIFO memory part 21, while the data are enlarged by the read data enlargement control circuit 23 when the same are read from the FIFO memory part 21, as hereinabove described.
With reference to FIG. 60, description is now made on enlargement/reduction of data in a memory device storing digitalized data which are obtained by converting data of images etc. to a series of digital data using two scanning directions of main and subscanning directions in order to process the data of images or the like. FIG. 60 is a block diagram showing the structure of a conventional memory device having a data enlargement/reduction function. Referring to FIG. 60, numeral 24 denotes a memory part capable of writing/reading data, and numeral 25 denotes a subscanning direction enlargement/reduction control circuit which enlarges/reduces data in the subscanning direction. This circuit forms a memory device having a subscanning direction enlargement/reduction function with the memory part 24. The memory part 24 comprises a memory cell matrix 12 which is formed by a plurality of memory cells for recording data, a write address decoder 14 which decodes address data Ad0 to Ad1 received from the exterior of the memory part 24 and specifies addresses of the memory cell matrix 12 for writing write data WD, a write data driver 15 which writes the write data WD in the memory cell matrix 12 in response to a clock WK1, a read address decoder 18 which decodes address data Ad0 to Ad1 outputted from the subscanning direction enlargement/reduction control circuit 25 and specifies positions of prescribed memory cells on the memory cell matrix 12 for reading data held in the memory cells, and a read data sense amplifier 19 for converting data read from the memory cell matrix 12 to a digital signal.
Operations of the memory device shown in FIG. 60 are now described with reference to FIGS. 61(a) and 61(b). In order to simplify the description, it is assumed that this memory devices enlarges/reduces data in data reading, and the memory cell matrix 12 holds 4-bit data in the main scanning direction. It is also assumed that the memory cell matrix 12 already holds "0001", "1011", "1000" and "1111" as data from addresses 0 to 15. This state is shown in FIG. 61(b). In order to read data in equal-scale magnification, the subscanning direction enlargement/reduction control circuit 25 outputs the address data Ad0 to Ad1 to the read address decoder 18 to successively increment the addresses one by one from the address 0. The read data sense amplifier 19 reads the data successively from the address 0 in response to a read clock RK1 along the addresses specified by the read address decoder 18. The read sense amplifier 19 outputs "0001", "1011", "1000" and "1111" as read data RD. This state is shown as "magnification:.times.1" in FIGS. 61(a) and 61(b).
In the case of enlargement magnification of 2, the subscanning direction enlargement/reduction control circuit 25 outputs the address data AD0 to AD1 to repeat the 4-bit data in the main scanning direction twice for successively specifying addresses 0 to 3, then repeatedly successively specifying the addresses 0 to 3, then successively specifying addresses 4 to 7, and then repeatedly successively specifying the addresses 4 to 7. The read data sense amplifier 19 successively reads the 4-bit data in the main scanning direction from the memory cell matrix 12 repeatedly from the address 0 in response to the read clock RK1 along the addresses specified by the read address decoder 18. Then, the read data sense amplifier 19 outputs "0001", "0001", "1011", "1011", . . . as the read data RD.
In the case of reduction magnification of 0.5, on the other hand, the subscanning direction enlargement/reduction control circuit 25 outputs the address data Ad0 to Ad1 to the read address decoder 18 to successively specify the addresses every other set of 4-bit data in the main scanning direction for specifying the addresses 0 to 3, then specifying the addresses 8 to 11 and then specifying the addresses 16 to 19. The read data sense amplifier 19 reads the addresses from the memory cell matrix 12 every other set of 4-bit data in the main scanning direction in response to the read clock RK1 along the addresses specified by the read address decoder 18 successively from the address 1 or 4. Then, the read data sense amplifier 19 outputs "0001", "1000" or "1011", "1111" as the read data RD.
In the conventional FIFO memory device having the aforementioned structure, the write data reduction control circuit 22 reduces data when the same are written in the FIFO memory part 21 while the read data enlargement control circuit 23 enlarges the data when the same are read from the FIFO memory part 21. Therefore, a data enlargement/reduction control circuit which is provided in the exterior of the FIFO memory part 21 is disadvantageously increased and complicated in logical scale depending on set conditions and the like, although the FIFO memory part 21 is simple in structure.
In the conventional memory device for enlarging/reducing data in two directions of main and subscanning directions having the aforementioned structure, further, an enlargement/reduction control circuit for controlling enlargement/reduction in the main or subscanning direction is disadvantageously increased in scale and complicated in circuit structure since the same must generate memory addresses responsive to situations depending on set magnification, conditions etc. for enlargement/reduction.